1. Field of the Invention
This invention is concerned with an in-circuit emulator, and especially relates to a data tracing apparatus used in an in-circuit emulator.
2. Description of the Related Art
An in-circuit emulator is used for developing programs of a system which includes a microcomputer. Such an emulator has a data tracing function to store data history of signals on the data bus for a predetermined period of time. Debugging of programs is performed with reference to the data history.
FIG. 5 is a block diagram showing the configuration of the trace function unit of a conventional in-circuit emulator. In this figure, reference numeral 1 denotes a target Central Processing Unit (CPU) to be subjected to program developing, 2 denotes a Static Random Access Memory (SRAM) for storing traced data of the bus signals of the target CPU 1, 3 denotes a counter which produces addresses for making access to the SRAM 2 based on strobe signal S1 output from the target CPU, 4 denotes a write signal generating unit which generates write signal W1 for writing data to SRAM 2 based on strobe signal S1 output from the target CPU 1.
FIG. 6 is a timing chart showing timings of the signals in the in-circuit emulator indicated in FIG. 5. In FIG. 6, reference (a) shows timing of the strobe signal S1 output from the target CPU 1 by each bus cycle, reference (b) shows timing of signal T1 to be traced such as signals on the bus of the target CPU 1 and control signals, reference (c) shows timing of address signal A1 output from counter 3 for making access to the SRAM 2, reference (d) shows timing of write signal W1 output from the write signal generating unit 4.
The target CPU 1 performs operations to memories and I/O devices by bus cycles in order to deal with a user program which is the subject of debugging. The target CPU 1 recognizes the bus cycle operations by monitoring strobe signal S1. Namely, the target CPU 1 recognizes that a bus cycle operation is performed each time strobe signal S1 becomes active. In the above configuration, the strobe signal S1 is designed to be low-active.
Strobe signal S1 output from the target CPU 1 is input to the counter 3 and the write signal generating unit 4. The counter 3 increments address signal A1 and outputs it at a trailing edge of the strobe signal S1. Namely, address signal A1 is incremented each time a bus cycle operation is performed by the target CPU 1 and address signal A1 is provided to the SRAM 2. On the other hand, the write signal generating unit 4 generates write signal W1 for writing data to the SRAM 2 based on strobe signal S1 and outputs write signal W1 to the SRAM 2. Signals indicative of the status of the target CPU 1 including address bus signals, data bus signals, and other control signals are provided to the data signal input terminal of the SRAM 2 as signals T1 to be traced. Therefore, the signals T1 to be traced are stored in the SRAM 2 successively.
The conventional in-circuit emulator is configured as explained above and it is necessary for such an emulator to include a SRAM with a large capacity, which leads to a high cost and a large size of the apparatus.